As technology nodes advance, smaller and smaller spaces are provided between the n-EPI and the p-EPI layers formed on adjacent fin structures. For example, in 7 nm structures the space for the n-EPI and p-EPI is generally only around 50 nm or less. This small spacing can lead to N-P shorting either between the n-EPI and p-EPI or between the n-EPI and the Vdd power supply layer for the adjacent device. For example, during epitaxial growth processes performed on the adjacent fins, variations can occur in the size of the epitaxial growth, or abnormal epitaxial growth can occur, which expands beyond the masks formed on the respective fins resulting in a merging of the epitaxial material.
An approach to resolving this issue is to reduce the growth time for the formation of the epitaxial layers on the fins since the actual size of the EPI layer is a function of the growth time. However, this can lead to the formation of inadequate EPI layers which, in turn, will restrict device performance, particularly since the EPI layers are used for forming the source and drain regions for finFET devices. Another approach to reduce the likelihood of shorting between the epitaxial layers of adjacent fin structures is to use remaining portions of sidewall spacers on the sides of the fins to constrain the epitaxial growth, since the space between the n-EPI and the p-EPI is insufficient for full EPI growth in 7 nm node technology. However, again, this results in an EPI volume which is significantly smaller than desirable, and thus restricts device performance.